1. Field of the Invention
This invention is in the field of integrated circuit memories. More particularly, it relates to an integrated circuit Static Random Access Memory ("SRAM") with improved recovery after writing characteristics to enable faster reading of the memory.
2. Description of the Relevant Art
Many types of SRAMs are now well known. Typically, an SRAM memory is fabricated on a semiconductor substrate as an array of memory cells. At present, integrated circuit technology allows fabricating about one million SRAM cells on a single chip.
FIG. 1 depicts a typical prior art static SRAM cell implemented using NMOS fabrication technology. The cell shown consists of a flip-flop of cross-coupled transistors 13 and 14 and access transistors 11 and 12. The access transistors are turned on when the word line is selected (raised in voltage) and they connect the flip-flop to the true Bit output line and the complement Bit output line, labelled herein as Bit and Bit, respectively. The access transistors act as transmission gates, allowing bidirectional current flow between the flip-flop and the Bit and Bit lines. To emphasize this point, the drains and sources of the access transistors are not distinguished. Transistors 15 and 16 act as a load for the memory cell, limiting the current flow through the cell.
To read or write a memory cell, the voltage of its word line is raised, thus turning on access transistors 11 and 12. In this way, one side of the cell flip-flop is connected to the Bit line and the other side is connected to the Bit line. Consider as an example the read operation for the cell in FIG. 1 and assume that the cell is storing a 0. In this case transistor 13 is on and transistor 14 is off. When transistors 11 and 12 are turned on, current flows from the Bit line through transistors 11 and 13 to ground. This causes the voltage of the Bit line to be pulled down slightly. Simultaneously, the Bit line is held high by a bit-line load structure (not shown). The resulting voltage difference between the Bit and Bit lines represents the state of the memory cell and is detected by a column sense amplifier (not shown). The magnitude of the voltage differential during reading operations is roughly 100 millivolts.
A write operation in the illustrated SRAM cell occurs in the following way. The information to be written and its complement are transferred to the Bit and Bit lines. Thus, if a 1 is to be written, the Bit line is held at V.sub.cc and the line is lowered to ground (V.sub.ss). The magnitude of the voltage differential between Bit and Bit during writing operations is typically several volts. The appropriate word line is then turned on. The conducting transistors 11 and 12 then cause the high voltage on the Bit line to appear at the gate of transistor 14 and the drain of transistor 13 and the low voltage on the Bit line to appear at the gate of transistor 13 and the drain of transistor 14. This state, which denotes a stored 1, will be maintained indefinitely unless changed by another write operation.
During reading operations, the finite currents available in transistors 11 and 12, the resistance of the bit lines load structure, and the capacitances of the Bit and Bit lines determine the fall and rise times of the signals on the Bit and Bit lines. These times, in turn, contribute to the access time of the SRAM. Typical signal timing characteristics are shown in FIG. 2.
To improve SRAM performance, attempts have been made to reduce these components of time delay. During reading operations, the reading time is determined by the time required for the voltages on the Bit and Bit to cross over or "exchange" their values. One method which reduces this time is changing the voltages of the Bit and Bit lines from the values acquired in the previous cycle to a value midway between those values while the signal on the word line is changing. Thus, as transistors 11 and 12 turn on, the Bit and Bit lines will have to charge and discharge less than if the Bit and Bit lines were to start from their extreme original values. In this way, the time taken for the memory cell to create a new voltage differential between Bit and Bit will be reduced. The lower set of waveforms in FIG. 2 illustrates the technique. The process is known as equilibration and precharge. It is controlled by a pulse automatically generated whenever a change in the row or word address inputs is detected. One problem with this method is that an extra circuit is required to detect the beginning of the reading operation and to short the Bit and Bit lines together. Such an extra circuit increases the complexity of the SRAM and uses valuable surface area on the integrated circuit.
Another technique for speeding circuit operation without equilibration and precharge is to decrease the resistance of the bit line load structure. Because the RC time constant created by bit line capacitances and the load structure resistance largely determines the rise and fall time of the voltages on the bit lines, decreasing the resistance of the load directly improves the speed of the memory. However, such a reduction in resistance also decreases the voltage differential between the bit lines, which can result in too small a voltage differential to allow for the cell to be read reliably.
The time required to re-establish the correct reading differential on the bit lines after a writing operation is an important factor in the speed of the SRAM. During writing, a voltage differential of several volts is established on the bit lines. To read the cell, this differential must be "recovered" to the approximately 100 millivolt maximum differential required for reading.
Write-recovery circuits which hasten removal of the voltage transients following a write operation are known. A write-recovery circuit "recovers" or forces the bit lines in the column to which data last was written to be within a predetermined voltage differential to permit reading. During a write operation, a write recovery circuit holds all bit lines at a high potential, other than the one bit line pulled low during the write. After the write operation, the recovery circuit pulls the low bit line up to the high potential.
A typical prior art write-recovery circuit is shown in FIG. 3. During a read operation, the circuit shown in FIG. 3 places all bit lines at the common high potential. The circuit detects when a write transition occurs, then generates an address transition pulse (ATP) which pulls the low bit line back up to the high potential. In the circuit shown in FIG. 3, transistors M1 and M2 short the bit lines to the high potential, Vcc, during a read operation. An ATP generator G1 activates transistors M3, M4 and M5 when an address transition occurs. Although only one ATP generator is shown in FIG. 3, it is possible to have more than one such generator in a given SRAM memory. Transistors M3 and M5 pull-up or "recover" the appropriate bit line Bit or Bit, and at the same time transistor M4 acts as a shunt to equalize the voltage between Bit and Bit. Because one of the bit lines is already at the high potential, transistor M4 causes both bit lines to be within a small voltage differential of one another, enabling a read operation to be performed.
Prior art circuits of the type shown in FIG. 3 have several disadvantages. Transistors M3 and M5 typically are relatively slow MOS devices resulting in relatively long recovery times. Furthermore, the width of the ATP pulse is critical: too narrow a pulse causes poor recovery and extended access time; too wide a pulse wastes time, slowing the entire memory system. In general, prior art circuits of the type shown in FIG. 3 are only capable of recovering in approximately 3 nanoseconds, and produce approximately 30 nanosecond system access time.
Other prior art circuits have been used to speed the bit line recovery to the differential voltage levels needed to read the memory cell. One such circuit is shown in FIG. 4. Each bit line Bit and Bit is selectively connected to a high potential V.sub.cc through series connected PMOS load transistors 41 and 42. At the beginning of a write cycle, the PMOS load transistors are on, placing all bit lines at the high potential. During a write operation the PMOS load transistors connected to the bit line Bit and the complement bit line Bit of the column containing the cell to be written are turned off, enabling the selected one of the Bit or Bit line to be pulled low, during which time data is written to the cell. For purposes of the remaining explanation we assume the Bit line was the selected line and the Bit line was not selected. After data is written to the cell, the nonselected bit line Bit is pulled down to an intermediate voltage by a bipolar clamp transistor (not shown) and a bipolar pull-up transistor 43 pulls the selected bit line Bit up to the intermediate voltage. As the selected line is pulled up, a shunt transistor 45 shunts it to the nonselected line to minimize the voltage differential between the two bit lines and hasten recovery. Simultaneously, PMOS load transistors 41 and 42, which are in series with both bit lines, are turned back on, returning the bit lines to the high potential. A sense amplifier circuit (not shown) connected to the column then may be used to read the cell contents. In one implementation of this method with a 32 column array, 64 pairs of bipolar junction pull-up transistors all have a common base node W2b. One problem with using this common base node bipolar junction transistor circuit is that, as one or the other bit line is pulled low in order to write to the selected memory cell, the bipolar junction transistor coupled to the other bit line, which bit line remains high, can experience reverse emitter-base breakdown when W2b is pulled low. To prevent this, the common base node must be clamped to a particular voltage. In one known implementation this problem was eliminated by creating the bipolar transistors with a material having a high reverse breakdown voltage. Using this material, however, also resulted in a slower transistor, reducing the benefit of the recovery circuit.
Thus, a need exists for a circuit which can reduce the time necessary for an SRAM memory cell to recover from writing, yet which does not suffer the common base node problems of the prior art circuits.